The Intel 8008 support page

Collect and share information and software about Intel's 8008 — the world's first 8 bit CPU, introduced April 1972

This site is neither operated nor maintained by Intel. Intel is a registered trademark of the Intel Corp, USA


Preface

When I was searching the web for information about the Intel 8008 a few years ago, little to none information was available. So I started collecting the bits spread around and began representing them here.

Meanwhile, the situation has changed. Wikipedia hosts an excellent article and a number of scanned datasheets are available.

Special thanks to Klemens Krause, who maintains a great computer museum that provided me lots of information and inspiration.

Some history

The Intel 8008 is the world's first 8 bit microprocessor introduced in April 1972. The 8008 was originally code named the 1201. The developers were Ted Hoff, Stan Mazor, Hal Feeney, and Federico Faggin.

Intel designed it for Computer Terminal Corporation (CTC) for use in it's Datapoint 2200 terminal, but because the 8008 was delivered too late and did not meet CTC's expectations, they didn't used it. Intel then brought the rights back and marketed the chip on it's own.

General description

The Intel 8008 runs at 0.5 MHz, the 8008-1 at 0.8 MHz. It contains 3500 transistors realized in PMOS technology at 10-micron. For comparison, an Intel Pentium 4 consists of 178.000.000 transistors manufactured in 0.13-micron.

It was used in dumb terminals, general calculators, bottling machines, and for general data/character manipulation.

The 8008 microprocessor contains an accumulator A plus 6 scratch registers B, C, D, E, H and L, each 8 bit wide. H & L acts as a pointer to memory, providing an virtual register M. This is the only way on the 8008 to access the memory.

Separate from the memory, 8 input ports and 24 output ports can be accessed.

The chip has a 8 bit wide data bus and 14 bit wide address bus, which can address 16 KB of memory. Since Intel could only manufacture 18 pin DIP packages at 1972, the bus has to be three times multiplexed. Therefore the chip's performance is very limited and it requires a lot external logic to decode all signals.

Very crude interrupt support is given, since the registers can't be pushed on the hardware stack. If you really need this, you could attach FIFO RAMs like the SN74LS222 or SN74ALS232 to an I/O port.

Though often heard, it's not true that the Intel 8008 would be "twice a Intel 4004" that was introduced one year before. The 4004 has a harvard architecture and 16 registers while the 8008 has a von Neumann architecture and 7 registers.

The 8008 family is also referred to as the MCS-8.

Intel 8008 registers and flags

The 8008 microprocessor contains an 8 bit wide accumulator A plus 6 scratch registers B, C, D, E, H and L, each 8 bit wide. H & L acts as a pointer to memory, providing an virtual register M. This is the only way on the 8008 to access the memory. H contains the high significant byte and L the lower significant byte of the 14 bit address.

Sign, Zero, Parity and Carry-flags are available though the 8008 has no flag register. These four flag bits can be tested with conditional JMP, CALL and RETurn instructions.

Intel 8008 instruction set

The instruction set of the Intel 8008 can be divided into 7 groups: the CPU control, Input and output, jump, call and return, load, arithmetic and the rotate group.

There are two sets of mnemonics resulting in identically binary values. The old mnemonics are the first one published at 1972. Intel changed the mnemonics around the year 1975. Both sets are described below. The old set is designed to simplify things, it consists of three characters which can be coded into 16 bits making a lookup-table very easy.

CPU control group

binaryoldnewDescription
0 0  0 0 0  0 0 xHLTHLT 
1 1  1 1 1  1 1 1HLTHLT 

Input and output group

binaryoldnewDescription
0 1  0 0 M  M M 1INPINport MMM
0 1  R R M  M M 1OUTOUTport RRMMM (RR <> 0)

Jump group

binaryoldnewDescription
0 1  x x x  1 0 0JMPJMPunconditionally jump
    
0 1  0 0 0  0 0 0JFCJNCJMP if  carry = 0
0 1  0 0 1  0 0 0JFZJNZJMP if result <> 0
0 1  0 1 0  0 0 0JFSJPJMP if   sign = 0 (positive)
0 1  0 1 1  0 0 0JFPJPOJMP if parity = odd
0 1  1 0 0  0 0 0JCJCJMP if  carry = 1
0 1  1 0 1  0 0 0JZJZJMP if result = 0
0 1  1 1 0  0 0 0JSJMJMP if   sign = 1 (negative)
0 1  1 1 1  0 0 0JPJPEJMP if parity = even

Call and return group

binaryoldnewDescription
0 1  x x x  1 1 0CALCALLunconditionally call subroutine
    
0 1  0 0 0  0 1 0CFCCNCCALL if  carry = 0
0 1  0 0 1  0 1 0CFZCNZCALL if result <> 0
0 1  0 1 0  0 1 0CFSCPCALL if   sign = 0 (positive)
0 1  0 1 1  0 1 0CFPCPOCALL if parity = odd
0 1  1 0 0  0 1 0CCCCCALL if  carry = 1
0 1  1 0 1  0 1 0CZCZCALL if result = 0
0 1  1 1 0  0 1 0CSCMCALL if   sign = 1 (negative)
0 1  1 1 1  0 1 0CPCPECALL if parity = even
    
0 0  x x x  1 1 1RETRETunconditionally return
    
0 0  0 0 0  0 1 1RFCRNCRET if  carry = 0
0 0  0 0 1  0 1 1RFZRNZRET if result <> 0
0 0  0 1 0  0 1 1RFSRPRET if   sign = 0 (positive)
0 0  0 1 1  0 1 1RFPRPORET if parity = odd
0 0  1 0 0  0 1 1RCRCRET if  carry = 1
0 0  1 0 1  0 1 1RZRZRET if result = 0
0 0  1 1 0  0 1 1RSRMRET if   sign = 1 (negative)
0 0  1 1 1  0 1 1RPRPERET if parity = even
    
0 0  A A A  1 0 1RSTRSTcall subroutine at adrs AAA000

Load group

binaryoldnewDescription
1 1  D D D  S S SLdsMOV d,sload d with content of s
1 1  D D D  1 1 1LdMMOV d,Mload d with content of Mem
1 1  1 1 1  s s sLMsMOV M,sload M with content of s
    
0 0  d d d  1 1 0LdIMVI dLoad register d with data
0 0  1 1 1  1 1 0LMIMVI MLoad Memory M with data b

Arithmetic group

binaryoldnewDescription
1 0  0 0 0  s s sADsADD sadd contents of s to A
1 0  0 0 0  1 1 1ADMADD Madd contents of M to A
0 0  0 0 0  1 0 0ADIADI badd constant b to A
    
1 0  0 0 1  s s sACsADC sadd contents of s + CY to A
1 0  0 0 1  1 1 1ACMADC Madd contents of M + CY to A
0 0  0 0 1  1 0 0ACIACI badd constant b + CY to A
    
1 0  0 1 0  s s sSUsSUB ssub contents of s from A
1 0  0 1 0  1 1 1SUMSUB Msub contents of M from A
0 0  0 1 0  1 0 0SUISUI bsub constant b from A
    
1 0  0 1 1  s s sSBsSBB ssub contents of s + CY from A
1 0  0 1 1  1 1 1SBMSBB Msub contents of M + CY from A
0 0  0 1 1  1 0 0SBISBI bsub constant b + CY from A
    
1 0  1 0 0  s s sNDsANA slogical AND of s and A to A
1 0  1 0 0  1 1 1NDMANA Mlogical AND of M and A to A
0 0  1 0 0  1 0 0NDIANI blogical AND of const b and A to A
    
1 0  1 0 1  s s sXRsXRA slogical XOR of s and A to A
1 0  1 0 1  1 1 1XRMXRA Mlogical XOR of M and A to A
0 0  1 0 1  1 0 0XRIXRI blogical XOR of const b and A to A
    
1 0  1 1 0  s s sORsORA slogical OR of s and A to A
1 0  1 1 0  1 1 1ORMORA Mlogical OR of M and A to A
0 0  1 1 0  1 0 0ORIORI blogical OR of const b and A to A
    
1 0  1 1 1  s s sCPsCMP scompare s with A, set flags
1 0  1 1 1  1 1 1CPMCMP Mcompare M with A, set flags
0 0  1 1 1  1 0 0CPICPI bcompare const b with A, set flags
    
0 0  d d d  0 0 0INdINR dincrement register d (d<>A)
0 0  d d d  0 0 1DCdDCR rdecrement register d (d<>A)

Rotate group

binaryoldnewDescription
0 0  0 0 0  0 1 0RLCRLCrotate content of A left
0 0  0 0 1  0 1 0RRCRRCrotate content of A right
0 0  0 1 0  0 1 0RALRALrotate content of A left through CY
0 0  0 1 1  0 1 0RARRARrotate content of A right through CY

Each I-instruction (immediate addressing mode) is followed by a second byte containing the data.
Each JMP- and CALL-instructions are followed by two bytes containing the address. The LSB follows first, then the MSB. Since the 8008 uses only 14 address lines, the most significant two bits are ignored.

Intel 8008 pinout

                        ____    ____ 
		      _|    \__/    |_ 
	     --> Vdd |_|1         18|_| Interrupt <--
		      _|            |_ 
	     <--> D7 |_|2         17|_| Ready <--
		      _|            |_ 
	     <--> D6 |_|3         16|_| Phase 1 <--
		      _|            |_ 
	     <--> D5 |_|4  Intel  15|_| Phase 2 <--
		      _|            |_
	     <--> D4 |_|5  8008   14|_| Sync  -->
		      _|            |_
	     <--> D3 |_|6         13|_| S0 -->
		      _|            |_
	     <--> D2 |_|7         12|_| S1 -->
		      _|            |_ 
	     <--> D1 |_|8         11|_| S2 -->
		      _|            |_ 
	     <--> D0 |_|9         10|_| Vcc <--
		       |____________|

    

Pin functions

D0-D7bi-directional address/data-bus.
Interrupt(input, active high). Interrupt request is generated by I/O devices.
Ready(input, active high). If pulled to Low, the CPU waits for slow memory.
Phase 1, Phase 2(input). Two-phase clock, non-overlapping. The microprocessor needs this to generate a four-phase-clock internally.
Sync(output, active high). Indicates that the current machine cycle is the opcode fetch cycle of an instruction execution
S0-S2(output, active high). Machine status-signals, described below
Vdd, VccProvide -9V at Vdd and +5V at Vcc to operate at TTL-levels

The 8008 machine states:

NameS2S1S0Function
wait000Wait for slow memory
T3001Data input/output (memory access)
T1010Less significant address byte
stop011Wait for interrupt (HLT)
T2100More significant address byte + cc2 + cc1
T5101Internal data transfer
T1I110Like T1, but interrupt recognized
T4111Internal data transfer

cc2 and cc1 provided at T2-state give more information about the T3-state:

Namecc2cc1Function
PCI00Instruction Cycle. The first byte (containing the opcode) is read from the memory
PCR10Read Cycle. Data or following parts of the opcode are read from the memory
PCC01Command Cycle. Input-Output-Instruction. Whether a byte shall be read or written depends on the address
PCW11Write Cycle. Write data to memory

Datasheets

Identify a 8008

The part's name varies depending on the manufacturer.

Vintage computers

Some early designs used the 8008. Follow the external links to get more informations about these computers.

Homebrew Computers

Cross Assemblers

BASIC interpreter

PL/M for the Intel 8008

Simulators and Emulators

Photo gallery of Intel 8008 chips (on other pages)

Prices at eBay

DatePriceLocationDescription
2005-11-07US $123.50Silverdale, WA, USAIntel C8008, date code 76xx
2005-11-06EUR 24.17Trier, GermanyMF8008R, military version by Microsystems International, date code 7439
2005-10-31EUR 26.50GermanyU808 by MME, NOS, yellow and green marking, east german clone
2005-10-01US $61.66Bouvancourt, FranceIntel C8008 CPU, date code 7512, Malaysia, NOS
2005-09-29US $60.00Newmarket (Toronto), CanadaIntel C8008 Processor, date code 7619, Philippines, grey ceramic DUP, one of the end pins broken, some scratches on the top
2005-09-08US $188.50Vermont, USAIntel 8008-1, gold plated ceramic DIP
2005-09-02US $47.23APO, AP, USAIntel C8008-1, date code 7701, Malaysia, guaranteed of being in excellent condition, authentic and functioning
2005-09-02US $42.00APO, AP, USAIntel C8008, date code 7729, Hong Kong, guaranteed of being in excellent condition, authentic and functioning
2005-08-03US $44.77Ottawa, ON, CanadaIntel C8008-1, Malaysia 1977, date code 7701, out of some ancient HP lab equipment (02640-60008)
2005-08-03US $56.55Ottawa, ON, CanadaIntel C8008-1, Phillipines 1976, date code 7640, out of some ancient HP lab equipment (02640-60008)
2005-08-02US $46.00Newmarket (Toronto), CanadaIntel C8008, grey ceramic DIP with gold leads, date code 7730, Hong Kong, pin 9 missing, part of the ceramic has chipped away
2005-07-08US $57.00APO, AP, USAIntel C8008-1 3157A, date code 7705, Malaysia, NOS
2005-07-08US $103.50APO, AP, USAIntel C8008 03398, date code 7740, Malaysia, NOS
2005-07-04EUR 36.50Fohrde, GermanyU808D by MME, east german clone
2005-06-26US $55.57Brighton, Michigan, USAIntel 8008-1

EPROM burner for Intel 1702A

The very first 8 bit CPU often ran its programs off the very first EPROMs: the Intel 1702 and Intel 1702A, each holding 256 Bytes.

They are very different compared to later, more common EPROMs so that it's very hard to find a programmer these days, that is capable of burning these beasts:

Martin Feberhard designed a new EPROM burner based on a modern microcontroller: MFeberhard 1702A Programmer. Have a look at the Yahoo group Altair Computer Club.