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The Intel 8008 support page

Collect and share information and software about Intel's 8008 — the world's first 8 bit CPU, introduced April 1972

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This site is neither operated nor maintained by Intel. Intel is a registered trademark of the Intel Corp, USA

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Preface

When I was searching the web for information about the Intel 8008 a few years ago, little to none information was available. So I started collecting the bits spread around and began representing them here.

Meanwhile, the situation has changed. Wikipedia hosts an excellent article and a number of scanned datasheets are available.

Special thanks to Klemens Krause, who maintains a great computer museum that provided me lots of information and inspiration.

Some history

The Intel 8008 is the world's first 8 bit microprocessor introduced in April 1972. The 8008 was originally code named the 1201. The developers were Ted Hoff, Stan Mazor, Hal Feeney, and Federico Faggin.

Intel designed it for Computer Terminal Corporation (CTC) for use in it's Datapoint 2200 terminal, but because the 8008 was delivered too late and did not meet CTC's expectations, they didn't used it. Intel then brought the rights back and marketed the chip on it's own.

General description

The Intel 8008 runs at 0.5 MHz, the 8008-1 at 0.8 MHz. It contains 3500 transistors realized in PMOS technology at 10-micron. For comparison, an Intel Pentium 4 consists of 178.000.000 transistors manufactured in 0.13-micron.

It was used in dumb terminals, general calculators, bottling machines, and for general data/character manipulation.

The 8008 microprocessor contains an accumulator A plus 6 scratch registers B, C, D, E, H and L, each 8 bit wide. H & L acts as a pointer to memory, providing an virtual register M. This is the only way on the 8008 to access the memory.

Separate from the memory, 8 input ports and 24 output ports can be accessed.

The chip has a 8 bit wide data bus and 14 bit wide address bus, which can address 16 KB of memory. Since Intel could only manufacture 18 pin DIP packages at 1972, the bus has to be three times multiplexed. Therefore the chip's performance is very limited and it requires a lot external logic to decode all signals.

Very crude interrupt support is given, since the registers can't be pushed on the hardware stack. If you really need this, you could attach FIFO RAMs like the SN74LS222 or SN74ALS232 to an I/O port.

Though often heard, it's not true that the Intel 8008 would be "twice a Intel 4004" that was introduced one year before. The 4004 has a harvard architecture and 16 registers while the 8008 has a von Neumann architecture and 7 registers.

The 8008 family is also referred to as the MCS-8.

Intel 8008 registers and flags

The 8008 microprocessor contains an 8 bit wide accumulator A plus 6 scratch registers B, C, D, E, H and L, each 8 bit wide. H & L acts as a pointer to memory, providing an virtual register M. This is the only way on the 8008 to access the memory. H contains the high significant byte and L the lower significant byte of the 14 bit address.

Sign, Zero, Parity and Carry-flags are available though the 8008 has no flag register. These four flag bits can be tested with conditional JMP, CALL and RETurn instructions.

Intel 8008 instruction set

The instruction set of the Intel 8008 can be divided into 7 groups: the CPU control, Input and output, jump, call and return, load, arithmetic and the rotate group.

There are two sets of mnemonics resulting in identically binary values. The old mnemonics are the first one published at 1972. Intel changed the mnemonics around the year 1975. Both sets are described below. The old set is designed to simplify things, it consists of three characters which can be coded into 16 bits making a lookup-table very easy.

CPU control group

binary	old	new	Description
0 0  0 0 0  0 0 x	HLT	HLT
1 1  1 1 1  1 1 1	HLT	HLT

Input and output group

binary	old	new	Description
0 1  0 0 M  M M 1	INP	IN	port MMM
0 1  R R M  M M 1	OUT	OUT	port RRMMM (RR <> 0)

Jump group

binary	old	new	Description
0 1  x x x  1 0 0	JMP	JMP	unconditionally jump
0 1  0 0 0  0 0 0	JFC	JNC	JMP if  carry = 0
0 1  0 0 1  0 0 0	JFZ	JNZ	JMP if result <> 0
0 1  0 1 0  0 0 0	JFS	JP	JMP if   sign = 0 (positive)
0 1  0 1 1  0 0 0	JFP	JPO	JMP if parity = odd
0 1  1 0 0  0 0 0	JC	JC	JMP if  carry = 1
0 1  1 0 1  0 0 0	JZ	JZ	JMP if result = 0
0 1  1 1 0  0 0 0	JS	JM	JMP if   sign = 1 (negative)
0 1  1 1 1  0 0 0	JP	JPE	JMP if parity = even

Call and return group

binary	old	new	Description
0 1  x x x  1 1 0	CAL	CALL	unconditionally call subroutine
0 1  0 0 0  0 1 0	CFC	CNC	CALL if  carry = 0
0 1  0 0 1  0 1 0	CFZ	CNZ	CALL if result <> 0
0 1  0 1 0  0 1 0	CFS	CP	CALL if   sign = 0 (positive)
0 1  0 1 1  0 1 0	CFP	CPO	CALL if parity = odd
0 1  1 0 0  0 1 0	CC	CC	CALL if  carry = 1
0 1  1 0 1  0 1 0	CZ	CZ	CALL if result = 0
0 1  1 1 0  0 1 0	CS	CM	CALL if   sign = 1 (negative)
0 1  1 1 1  0 1 0	CP	CPE	CALL if parity = even
0 0  x x x  1 1 1	RET	RET	unconditionally return
0 0  0 0 0  0 1 1	RFC	RNC	RET if  carry = 0
0 0  0 0 1  0 1 1	RFZ	RNZ	RET if result <> 0
0 0  0 1 0  0 1 1	RFS	RP	RET if   sign = 0 (positive)
0 0  0 1 1  0 1 1	RFP	RPO	RET if parity = odd
0 0  1 0 0  0 1 1	RC	RC	RET if  carry = 1
0 0  1 0 1  0 1 1	RZ	RZ	RET if result = 0
0 0  1 1 0  0 1 1	RS	RM	RET if   sign = 1 (negative)
0 0  1 1 1  0 1 1	RP	RPE	RET if parity = even
0 0  A A A  1 0 1	RST	RST	call subroutine at adrs AAA000

Load group

binary	old	new	Description
1 1  D D D  S S S	Lds	MOV d,s	load d with content of s
1 1  D D D  1 1 1	LdM	MOV d,M	load d with content of Mem
1 1  1 1 1  s s s	LMs	MOV M,s	load M with content of s
0 0  d d d  1 1 0	LdI	MVI d	Load register d with data
0 0  1 1 1  1 1 0	LMI	MVI M	Load Memory M with data b

Arithmetic group

binary	old	new	Description
1 0  0 0 0  s s s	ADs	ADD s	add contents of s to A
1 0  0 0 0  1 1 1	ADM	ADD M	add contents of M to A
0 0  0 0 0  1 0 0	ADI	ADI b	add constant b to A
1 0  0 0 1  s s s	ACs	ADC s	add contents of s + CY to A
1 0  0 0 1  1 1 1	ACM	ADC M	add contents of M + CY to A
0 0  0 0 1  1 0 0	ACI	ACI b	add constant b + CY to A
1 0  0 1 0  s s s	SUs	SUB s	sub contents of s from A
1 0  0 1 0  1 1 1	SUM	SUB M	sub contents of M from A
0 0  0 1 0  1 0 0	SUI	SUI b	sub constant b from A
1 0  0 1 1  s s s	SBs	SBB s	sub contents of s + CY from A
1 0  0 1 1  1 1 1	SBM	SBB M	sub contents of M + CY from A
0 0  0 1 1  1 0 0	SBI	SBI b	sub constant b + CY from A
1 0  1 0 0  s s s	NDs	ANA s	logical AND of s and A to A
1 0  1 0 0  1 1 1	NDM	ANA M	logical AND of M and A to A
0 0  1 0 0  1 0 0	NDI	ANI b	logical AND of const b and A to A
1 0  1 0 1  s s s	XRs	XRA s	logical XOR of s and A to A
1 0  1 0 1  1 1 1	XRM	XRA M	logical XOR of M and A to A
0 0  1 0 1  1 0 0	XRI	XRI b	logical XOR of const b and A to A
1 0  1 1 0  s s s	ORs	ORA s	logical OR of s and A to A
1 0  1 1 0  1 1 1	ORM	ORA M	logical OR of M and A to A
0 0  1 1 0  1 0 0	ORI	ORI b	logical OR of const b and A to A
1 0  1 1 1  s s s	CPs	CMP s	compare s with A, set flags
1 0  1 1 1  1 1 1	CPM	CMP M	compare M with A, set flags
0 0  1 1 1  1 0 0	CPI	CPI b	compare const b with A, set flags
0 0  d d d  0 0 0	INd	INR d	increment register d (d<>A)
0 0  d d d  0 0 1	DCd	DCR r	decrement register d (d<>A)

Rotate group

binary	old	new	Description
0 0  0 0 0  0 1 0	RLC	RLC	rotate content of A left
0 0  0 0 1  0 1 0	RRC	RRC	rotate content of A right
0 0  0 1 0  0 1 0	RAL	RAL	rotate content of A left through CY
0 0  0 1 1  0 1 0	RAR	RAR	rotate content of A right through CY

Each I-instruction (immediate addressing mode) is followed by a second byte containing the data.
Each JMP- and CALL-instructions are followed by two bytes containing the address. The LSB follows first, then the MSB. Since the 8008 uses only 14 address lines, the most significant two bits are ignored.

Intel 8008 pinout

                        ____    ____
		      _|    \__/    |_
	     --> Vdd |_|1         18|_| Interrupt <--
		      _|            |_
	     <--> D7 |_|2         17|_| Ready <--
		      _|            |_
	     <--> D6 |_|3         16|_| Phase 1 <--
		      _|            |_
	     <--> D5 |_|4  Intel  15|_| Phase 2 <--
		      _|            |_
	     <--> D4 |_|5  8008   14|_| Sync  -->
		      _|            |_
	     <--> D3 |_|6         13|_| S0 -->
		      _|            |_
	     <--> D2 |_|7         12|_| S1 -->
		      _|            |_
	     <--> D1 |_|8         11|_| S2 -->
		      _|            |_
	     <--> D0 |_|9         10|_| Vcc <--
		       |____________|

    

Pin functions

D0-D7	bi-directional address/data-bus.
Interrupt	(input, active high). Interrupt request is generated by I/O devices.
Ready	(input, active high). If pulled to Low, the CPU waits for slow memory.
Phase 1, Phase 2	(input). Two-phase clock, non-overlapping. The microprocessor needs this to generate a four-phase-clock internally.
Sync	(output, active high). Indicates that the current machine cycle is the opcode fetch cycle of an instruction execution
S0-S2	(output, active high). Machine status-signals, described below
Vdd, Vcc	Provide -9V at Vdd and +5V at Vcc to operate at TTL-levels

The 8008 machine states:

Name	S2	S1	S0	Function
wait	0	0	0	Wait for slow memory
T3	0	0	1	Data input/output (memory access)
T1	0	1	0	Less significant address byte
stop	0	1	1	Wait for interrupt (HLT)
T2	1	0	0	More significant address byte + cc2 + cc1
T5	1	0	1	Internal data transfer
T1I	1	1	0	Like T1, but interrupt recognized
T4	1	1	1	Internal data transfer

cc2 and cc1 provided at T2-state give more information about the T3-state:

Name	cc2	cc1	Function
PCI	0	0	Instruction Cycle. The first byte (containing the opcode) is read from the memory
PCR	1	0	Read Cycle. Data or following parts of the opcode are read from the memory
PCC	0	1	Command Cycle. Input-Output-Instruction. Whether a byte shall be read or written depends on the address
PCW	1	1	Write Cycle. Write data to memory

Datasheets

• MCS-8 at bitsavers
• Various documents are at Bryan's Old Computers and at the bottom of 8008chron.com.

Identify a 8008

The part's name varies depending on the manufacturer.

• Intel

  D8008-1 e.g. lets you know:

  1. Package type
     • C = Side-brazed ceramic DIP
     • D = ceramic DIP
     • P = Plastic DIP
  2. Part number 8008
  3. Frequency
     • blank = 0.5 MHz
     • -1 = 0.8 MHz

• Microsystems International

  MF8008R = 0.5 MHz, MF8008-1R = 0.8 MHz, 18-pin ceramic DIP, Gray ceramic/gold top/gold pins - no further information available.

• 8008 by Siemens

  SAB8008-1C = 0.8 MHz, 18-pin ceramic DIP, Purple ceramic/gold top/gold pins- no further information available.

• Clones by east german VEB Funkwerk Erfurt

  The equivalent name is U808D or VB808D for the military version, both running at 0.5 MHz - no further information available.

Vintage computers

Some early designs used the 8008. Follow the external links to get more informations about these computers.

• Mark-8
  • The Mark-8 at oldcomputers.com
  • Mark-8 Minicomputer
  • A Mark-8 Experience
  • The Mark-8 Minicomputer
• MCM 70/700
  • The Micro Computer Machines MCM/70
  • MCM Model 782 APL
• NBI Hantu
• R2E Micral
• Robotron K 1510 / PBT 4000
  • Robotron PBT4000, robotrontechnik.de (German)
  • Robotron K1510, Museum FH-Brandenburg (German)
• Scelbi 8H, Scelbi 8B
  • SCELBI Computer Museum
  • Scelbi 8H, Scelbi 8B
  • The 8008 and Scelbi
  • SCELBI's Wikipedia page
• MIL MOD-8 and GNC-8
• Bill-1 by Litton Data Systems

Homebrew Computers

• emuf08 (German)
• 8008 Computer "Clock"
• SCELBI 2002
• LC-8008

Cross Assemblers

• The Macroassembler AS by Alfred Arnold has been my favorite assembler for many years. It's latest version supports the 8008 now, with both old and new instruction sets. AS is available for almost any platform a C compiler exists for.
• SB-Assembler is a free cross-assembler supporting a lot of CPUs including the 8008
• AS8 by Thomas E. Jones is a small 8008 Assembler written in ANSI-C, source code is available, as well as a Windows executable. The original web pages The Mark-8 Minicomputer and AS8 User's Manual are offline.

BASIC interpreter

• SCELBAL is a BASIC interpreter written in assembler, published by SCELBI COMPUTER Consulting, Inc.
  8008chron.com hosts another version of the code.

PL/M for the Intel 8008

• Gary Kildall programmed a PL/I compiler for the 8008 in FORTRAN and called it PL/M. I wish, that compiler would appear somewhere...

Simulators and Emulators

• SIMH, emulates a lot of historic computers including a SCELBI-8B
• 8008 Simulation In JavaScript running SCELBAL
• Semi-Decent 8008 Emulator
• 8008/SCELBI OS/X Emulator Program
• Sim8008 by Andreas Gebhardt, Simulator with assembler and debugger for Windows, in German only

Photo gallery of Intel 8008 chips (on other pages)

• cpu-zone.com - watch'em all! ;-)
• cpu-world.com
• cpu-collection.de
• Ken Shirriff's blog -- Die photos and analysis

Prices at eBay

Date	Price	Location	Description
2005-11-07	US $123.50	Silverdale, WA, USA	Intel C8008, date code 76xx
2005-11-06	EUR 24.17	Trier, Germany	MF8008R, military version by Microsystems International, date code 7439
2005-10-31	EUR 26.50	Germany	U808 by MME, NOS, yellow and green marking, east german clone
2005-10-01	US $61.66	Bouvancourt, France	Intel C8008 CPU, date code 7512, Malaysia, NOS
2005-09-29	US $60.00	Newmarket (Toronto), Canada	Intel C8008 Processor, date code 7619, Philippines, grey ceramic DUP, one of the end pins broken, some scratches on the top
2005-09-08	US $188.50	Vermont, USA	Intel 8008-1, gold plated ceramic DIP
2005-09-02	US $47.23	APO, AP, USA	Intel C8008-1, date code 7701, Malaysia, guaranteed of being in excellent condition, authentic and functioning
2005-09-02	US $42.00	APO, AP, USA	Intel C8008, date code 7729, Hong Kong, guaranteed of being in excellent condition, authentic and functioning
2005-08-03	US $44.77	Ottawa, ON, Canada	Intel C8008-1, Malaysia 1977, date code 7701, out of some ancient HP lab equipment (02640-60008)
2005-08-03	US $56.55	Ottawa, ON, Canada	Intel C8008-1, Phillipines 1976, date code 7640, out of some ancient HP lab equipment (02640-60008)
2005-08-02	US $46.00	Newmarket (Toronto), Canada	Intel C8008, grey ceramic DIP with gold leads, date code 7730, Hong Kong, pin 9 missing, part of the ceramic has chipped away
2005-07-08	US $57.00	APO, AP, USA	Intel C8008-1 3157A, date code 7705, Malaysia, NOS
2005-07-08	US $103.50	APO, AP, USA	Intel C8008 03398, date code 7740, Malaysia, NOS
2005-07-04	EUR 36.50	Fohrde, Germany	U808D by MME, east german clone
2005-06-26	US $55.57	Brighton, Michigan, USA	Intel 8008-1

EPROM burner for Intel 1702A

The very first 8 bit CPU often ran its programs off the very first EPROMs: the Intel 1702 and Intel 1702A, each holding 256 Bytes.

They are very different compared to later, more common EPROMs so that it's very hard to find a programmer these days, that is capable of burning these beasts:

• Simple 1702A EPROM Programmer by Stephen H. Lafferty

Martin Feberhard designed a new EPROM burner based on a modern microcontroller: MFeberhard 1702A Programmer. Have a look at the Yahoo group Altair Computer Club.

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